Cache Associativity
Definition
Cache associativity describes how many locations (ways) within a single cache set a given memory address is permitted to occupy. A cache of higher associativity can tolerate more aliasing across ways but requires additional tag storage and lookup logic per access.
Role in Parameterized Processor Design
In modern RTL design, cache associativity is treated as a first-class microarchitectural parameter that is exposed alongside other configuration knobs. A representative example from RISC-V RTL implementation practice lists cache associativity among the configurable "Microarchitectural Knobs" of a hyper-parameterizable core:
"We architect for ... Microarchitectural Knobs: Configurable pipeline depth, branch predictor structures (BHT vs. BTB sizes), cache associativity, and bus interfaces (AXI, AHB, TL-UL)."
This framing places cache associativity within the broader discipline of parameterization of processor IP, where PPA (performance, power, area) trade-offs are explored by sweeping parameters rather than committing to fixed values.
Cache Associativity in ASIP Simulation Studies
Cache associativity is one of the standard outputs reported by application-specific instruction-set processor (ASIP) cache simulators when evaluating memory hierarchies for specific workloads. In one such study (ArXiv 1406.5000), the simulators SimpleScalar and VEX were used to simulate cache memory design, and the reported cache-related results included:
- cache name
- sets
- cache associativity
- cache block size
- cache replacement policy
These parameters are swept according to the desired application, allowing the designer to choose an associativity (and accompanying block size and replacement policy) appropriate to the workload.
Cache Associativity in DRAM Cache Design over NVMM
In hybrid memory systems that pair DRAM with Non-Volatile Main Memory (NVMM) such as Intel Optane AEP DIMMs, cache associativity is one of the design parameters of the DRAM cache whose values must be determined empirically because the underlying device parameters are not published. In the system measurement study of ArXiv 2009.14469, the authors:
- measured performance and architecture features of AEP DIMM,
- explored the design of DRAM cache as part of a DRAM-AEP hybrid memory system, and
- reported the current design parameters of the DRAM cache, including "tag organization, cache associativity and set index mapping," with the paper stating these were "first published on academic paper."
Related Concept
- Parameterization — Cache associativity is typically exposed as a parameter in parameterized RTL designs and in ASIP configuration sweeps, rather than being fixed at design time.