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Branch Conditional (bc) Instruction

Concept WIKI v1 · 7/9/2026

The Branch Conditional (bc) instruction is a processor branch operation whose behavior can be influenced by the Condition Register (CR). Automated architectural-knowledge extraction, using a decision-tree classifier over collected instruction samples, has identified the specific operand encodings and CTR values that determine when a bc instruction is affected by CR.

Branch Conditional (bc) Instruction

Overview

The Branch Conditional (bc) instruction is a conditional branch operation found in instruction-set architectures. Its execution path can be governed by flag values held in the Condition Register (CR), meaning that depending on operand encodings (and, in special cases, the CTR register contents), the instruction either always reads and is affected by the CR, or only sometimes is.

Operands and Influencing State

The bc instruction carries two key operand fields that determine its CR-affected behavior:

  • bo.data — the branch-options operand field.
  • bi.data — the bit-index operand field that selects which CR bit is tested.

In addition, the value of the CTR (Count Register) can be a determining factor in certain special encodings of bo.data.

Classification-Derived Rules for CR Dependence

A sample-driven approach using a decision-tree classifier on execution traces produced the following architectural rules describing when a bc instruction is affected by the CR (claim "CR.Affected = True"):

Rule Probability of CR-Affected Sample Evidence
opcode in {bc}bo.data in {0x0, 0x1, 0x8, 0x9}CTR ≠ 0x0000000000000001 always (100%) 209 / 209 attempts
opcode in {bc}bo.data in {0x4, 0x5, 0x6, 0x7, 0xC, 0xD, 0xE, 0xF} always (100%) 952 / 952 attempts
opcode in {bc} (all other encodings) sometimes (47%) 1193 / 2486 attempts

These rules illustrate that a subset of bo.data values (e.g., 0x0–0x1, 0x8–0x9, 0x4–0x7, 0xC–0xF) cause the branch decision to always consult the CR, while remaining encodings produce mixed behavior dependent on other microarchitectural state.

Method of Discovery

The CR-affected rules above were discovered automatically rather than hand-authored. The procedure:

  1. Generate a bc instruction sample, varying its operands and surrounding register state.
  2. Collect input-feature information (opcode, operand fields such as bo.data / bi.data, register values such as CTR, MSR flags, etc.).
  3. Execute the instruction on a reference model / simulator.
  4. Determine whether the instruction's operation was affected by CR by toggling the relevant CR flag, re-executing, and comparing simulated machine states — flag-driven divergence indicates the instruction reads and is affected by the flag.
  5. Feed collected (features, CR-affected?) samples to a decision-tree classifier that deduces the input-feature combinations predicting CR-affected behavior.
  6. Translate the classifier's rules into a generator-usable form so that subsequent instruction-generation requests satisfying those rules will reproduce the CR-affected event with the requested probability.

This automated architectural-knowledge extraction enables test generators to construct interesting sequences such as an instruction that writes to CR followed by a bc branch that is provably affected by CR.

Representative Sample Rows

The following rows illustrate the feature set and the corresponding CR-affected outcome observed in collected samples:

opcode CTR MSR.VMX MSR.VSX bi.data bi.data==bo.data bi.data==branchBdRelative.bdDisplacementRef.data bo.data bo.data==branchBdRelative.bdDisplacementRef.data branchBdRelative.bdDisplacementRef.data CR.Affected
bc 147DB9BE3C4F54AE 0x1 0x0 0x7 False False 0x1B False 0xBAC4 False
bc none 0x1 0x0 0x13 False False 0xC False 0x5E84 True
bc none 0x0 0x1 0x0 0x1E False False 0x1C False 0x8DFC
bc 77B3EB82A79393A1 0x1 0x0 0x5 False False 0x1A False 0xD30 False

The sample table shows that, for example, bo.data == 0xC correlates with CR.Affected == True, consistent with the always-affected rule for bo.data ∈ {0x4,0x5,0x6,0x7,0xC,0xD,0xE,0xF}.

Significance

Automatically deriving when a bc branch depends on the CR is valuable for generation-based verification because it removes the need for a verification engineer to hand-encode the architecture's branch-conditional semantics, and it lets the generator deliberately produce CR-influencing branch sequences to stress test pipelines and branch-prediction logic.

CITATIONS

6 sources
6 citations
[1] The bc (branch conditional) instruction can be affected by the Condition Register (CR), and this dependence was automatically determined by a classifier over collected instruction samples. Automatic identification of information useful for generation-based ...
[2] When opcode is bc and bo.data is in {0x0,0x1,0x8,0x9} and CTR is not 0x0000000000000001, the instruction is always (100%) affected by CR (209/209 attempts). Automatic identification of information useful for generation-based ...
[3] When opcode is bc and bo.data is in {0x4,0x5,0x6,0x7,0xC,0xD,0xE,0xF}, the instruction is always (100%) affected by CR (952/952 attempts). Automatic identification of information useful for generation-based ...
[4] For opcode bc in all other encodings, CR-affected behavior occurs sometimes (47%, 1193/2486 attempts). Automatic identification of information useful for generation-based ...
[5] CR-affected status is determined by toggling a CR flag, re-executing the instruction on a simulator, and comparing simulated machine states — divergence indicates the instruction reads and is affected by the flag. Automatic identification of information useful for generation-based ...
[6] Sample rows demonstrate bc execution with varying CTR, MSR, bi.data, bo.data, and CR.Affected outcomes, supporting the classifier's identified rules. Automatic identification of information useful for generation-based ...