Bit Vector Stimuli

Bit vector stimuli are a form of simulation input used in processor verification, where test data are represented as bit vectors and applied directly to the input ports of a processor under verification.^[1] They are one of multiple stimulus representations used in simulation-based verification; another common form is executable programs loaded into program memory.^[1]

Role in simulation-based processor verification

In simulation-based verification of processors, stimuli are generated and applied to the design under verification, while verification tools monitor achieved functional coverage to assess verification completeness.^[1] A contemporary approach described in the literature uses pseudorandom generators (PRGs) to produce such stimuli.^[1]

Bit vector stimuli fit into this workflow as low-level input patterns:

1. A stimulus generator produces bit-vector values.
2. The bit vectors are applied to processor input ports.
3. The processor simulation executes under those inputs.
4. Coverage feedback is collected.
5. The generated stimuli are evaluated according to the coverage they achieve.^[1]

Contrast with program-based stimuli

The cited verification work distinguishes at least two stimulus representations for processors:^[1]

This distinction is important because the stimulus representation affects how the design is exercised. Bit vector stimuli operate at the input-port level, while program stimuli operate through the processor’s instruction execution path.^[1]

Generation using pseudorandom methods

Bit vector stimuli may be generated using pseudorandom generators as part of a coverage-driven verification process.^[1] In the cited work, PRG constraints are dynamically altered by a recurrent neural network that receives coverage feedback from simulation.^[1] Although the paper discusses stimuli generally, bit vectors are explicitly identified as one possible representation of those stimuli.^[1]

Coverage-driven optimization

The verification technique described in the evidence uses coverage feedback to improve stimulus generation. A recurrent neural network adjusts constraints for a pseudorandom generator based on observed coverage of the design under verification.^[1] Experimental results reported in that work indicate two outcomes relevant to stimulus generation:

• Coverage closure is achieved sooner than with the baseline approach described by the authors.^[1]
• A small set of high-coverage stimuli can be isolated and reused for regression testing.^[1]

For bit vector stimuli, this implies that not all generated input vectors are equally valuable: some bit-vector patterns may exercise significantly more functionality than others and can therefore be retained as compact regression assets.

Use in regression testing

A practical benefit of coverage-guided stimulus selection is the ability to identify a reduced set of stimuli that still achieves high coverage.^[1] When the stimuli are represented as bit vectors, such a reduced set can be reapplied to processor input ports during later regression runs to check whether previously covered functionality remains correct.

See also

• Processor verification
• Simulation-based verification
• Pseudorandom stimulus generation
• Coverage-driven verification
• Recurrent neural networks in verification

References

^[1]: Martin Fajčík et al., Automation of Processor Verification Using Recurrent Neural Networks, arXiv:1803.09810, DOI: 10.48550/arXiv.1803.09810. Evidence excerpt: the paper states that processor verification stimuli may be represented “by bit vectors applied to the input ports of the processor” or by programs loaded into program memory, and describes PRG-based stimulus generation guided by coverage feedback from simulation.