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Automated Random Test Generator

Concept WIKI v1 · 5/25/2026

An **automated random test generator** is a verification tool or methodology that creates randomized microcode or instruction test sequences to exercise a processor design. In modern microprocessor verification, these generators have increasingly replaced hand-written directed tests because processor complexity has grown and directed tests are less effective at covering large stimulus spaces.[^src]

Automated Random Test Generator

An automated random test generator is a verification tool or methodology that creates randomized microcode or instruction test sequences to exercise a processor design. In modern microprocessor verification, these generators have increasingly replaced hand-written directed tests because processor complexity has grown and directed tests are less effective at covering large stimulus spaces.[1]

Purpose

Automated random test generators are used to produce instruction streams that distribute stimulus across meaningful values of opcodes and instruction attributes. Their goal is to improve coverage of the verification stimulus space while allowing biasing toward important corner cases.[1]

In the described approach, the generator uses hierarchical constrained-random generation with the Synopsys VCS constraint solver to improve generation speed, reduce memory consumption, and control distributions of generated instruction types and attributes.[1]

Background

Traditional random instruction generation methods often randomize instruction fields sequentially. This can lead to verbose and redundant generated code, and it may provide limited control over the statistical distribution of instruction attributes.[1]

SystemVerilog constraint-language constructs provide a more concise way to describe microcode instructions as combinations of legal attributes. They also allow precise control over value distributions for individual fields.[1]

Architecture

The generator architecture described by Tang, Bahl, Wakefield, and Ramachandran consists of two layers:[1]

  1. Upper generator layer
    Implemented with a SystemVerilog random sequence construct. It uses weighted controls, or “knobs,” to determine the distribution of high-level generated items.[1]

  2. Lower opcode layer
    Implemented as an opcode class that is randomized with additional constraints and weights supplied by the upper layer.[1]

Tests are represented as sets of weighted values that direct the generator toward a required mix of instructions. The constraint solver applies these weights to control the distribution of opcode types produced by the generator.[1]

Single-Class Randomization

A simple implementation style places all opcode definitions and constraints in a single class. This approach is flexible because constraints can be applied between any data members of the opcode class.[1]

However, the single-class method can be slow because it presents the constraint solver with many random variables and a large set of constraints. In the reported prototype, the opcode class contained approximately 100 random variables and 800 constraint equations.[1]

In this design, one key random data member is the opcode type, which determines the kind of instruction generated. The class uses implication constraints to ensure that only legal opcodes are produced.[1]

Hierarchical / Multi-Class Randomization

To reduce the size of the constraint-solving problem, the opcode class can be divided into multiple smaller classes. The described object-oriented implementation uses a base class containing global constraints that apply to all opcodes. Derived subclasses then define groups of related opcodes with similar constraints.[1]

This hierarchical partitioning reduces the amount of constraint information that must be considered for each randomization problem. According to the cited implementation, splitting constraints into smaller opcode groups drastically reduced memory requirements and improved performance.[1]

Advantages

The hierarchical constrained-random approach provides several advantages over sequential randomization and monolithic single-class randomization:

  • More efficient coverage of opcode and instruction-attribute stimulus space.[1]
  • Better control over value distributions for individual fields.[1]
  • Ability to bias generation toward corner cases.[1]
  • Reduced memory requirements through hierarchical constraint partitioning.[1]
  • Improved randomization performance compared with a large single-class constraint problem.[1]

Implementation Technologies

The approach relies on:

  • SystemVerilog constraints, used to describe legal combinations of instruction attributes and control field distributions.[1]
  • SystemVerilog random sequence constructs, used in the upper generator layer to control weighted high-level item selection.[1]
  • Synopsys VCS constraint solver, used to solve the constrained-random generation problem and apply distribution weights.[1]

References

[1]: Gregory Tang and Rajat Bahl, AMD, Inc.; Alex Wakefield and Padmaraj Ramachandran, Synopsys Inc. Evidence record 4de14aa6-a0c6-4115-8dcd-2be6148018dc.