Assertion-based Monitoring

1. Definition and Scope

Assertion-based monitoring is a verification methodology in which formal or runtime assertions, together with coverage models, are embedded into a simulation or verification environment so that behavioral properties are continuously checked as the design-under-test (DUT) executes. In the context of functional faithfulness verification, assertion-based monitoring extends bit-level state comparison by ensuring that all relevant architectural features, pipeline events, and hazard conditions are exercised and checked.

2. Role in Functional Faithfulness Verification

Within the methodology exemplified by SupeRFIVe and UVM-TLM frameworks for RISC-V, parallel simulation of a DUT and an instruction-set simulator (ISS) yields state tuples (program counter, registers, memory, CSRs) that are compared per commit event. Assertion-based monitoring operates alongside this comparison pipeline to:

• Encode design intent as assertions that fire on defined events (e.g., instruction commit, exception entry, hazard detection).
• Drive coverage models for instructions, pipeline events, and assertions so that untested features and hazard scenarios are explicitly reported.
• Track key metrics such as instruction coverage, functional coverage, error detection rate, and throughput.

By coupling assertions with coverage feedback, the verification environment ensures that bit-wise discrepancy detection at observable boundaries is complemented by behavioral checks over architectural corner cases.

3. Relationship to Lockstep Simulation

Assertion-based monitoring is commonly deployed as part of lockstep simulation flows. In such flows, the DUT and ISS advance together while assertions embedded in the DUT sidecar or the verification testbench evaluate properties at each significant event. The combined scheme—parallel state comparison plus embedded assertions—provides both immediate detection of state mismatches and confirmation that intended behaviors are preserved.

4. Integration with Coverage Models

Coverage models for assertion-based monitoring serve two purposes:

1. Feature coverage: confirm that every architectural feature (e.g., specific CSR transitions, pipeline hazard classes) has been exercised by at least one assertion firing or success path.
2. Hazard coverage: confirm that hazard-detection paths have been activated under stimulus that triggers their conditions.

These coverage results are reported alongside throughput and error detection metrics, enabling closure of verification sign-off criteria.

5. Summary

Assertion-based monitoring augments state-level verification by providing continuous, event-driven checking of behavioral properties and by feeding coverage metrics that demonstrate which architectural features and hazard conditions have been tested. It is naturally combined with lockstep simulation to deliver comprehensive functional faithfulness verification.