ARM V6 Instruction Set

Concept

The ARM V6 (ARM Version 6) instruction set is the target instruction set architecture (ISA) modeled and verified in the context of the SimSoC full-system simulator and the 'Towards Verified Faithful Simulation' work. The ARMv6 architecture defines 147 instructions whose binary encodings, assembly syntax, and operational semantics are extracted semi-automatically from the ARM Architecture Reference Manual and formalized in the Coq proof assistant, with a corresponding C-based ISS in which each instruction is implemented as a standalone C function verified against the formal model using CompCert C semantics.

First seen 6/7/2026

Last seen 6/7/2026

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ARM V6 Instruction Set

The ARM V6 (also referred to in the evidence as ARM Version 6 or ARMv6) instruction set is the instruction set architecture (ISA) at the center of a formal-verification effort targeting the SimSoC full-system simulator. Within SimSoC, the ARM V6 ISS executes embedded applications by fetching, decoding, and executing real binary code; in the first dynamic-translation mode considered by the verification work, each ARM V6 instruction is translated into a C structure that has an associated semantics function, and it is these C semantic functions that are being verified.

Architecture Reference and Formal Model Construction

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SimSoC ← implements 95% 1e

SimSoC includes an ARM Version 6 ISS

Towards Verified Faithful Simulation ← uses 95% 1e

The paper verifies the ARM V6 instruction set simulator

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SimSoC IMPLEMENTS Extracted graph relationship

Towards Verified Faithful Simulation USES Extracted graph relationship

CITATIONS

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11 citations — click to expand

[1] The ARM Version 6 ISS is the verification target integrated within SimSoC, a full system simulator of System-on-Chips available as open source software. Towards Verified Faithful Simulation

[2] In the first dynamic-translation mode of SimSoC, the binary decoder translates each ARM V6 instruction into a C structure that has a semantics function, and it is these C semantic functions that are verified. Towards Verified Faithful Simulation

[3] There are 147 ARM instructions in the ARM V6 architecture; for each, the manual provides an encoding table, syntax, a piece of pseudo-code explaining its operation, exceptions, usage, and notes. Towards Verified Faithful Simulation

[4] The formal model of the ARM architecture in Coq is derived from the architecture reference manual in three automated steps: extracting information from the PDF, parsing the data into abstract syntax trees, and automated translation from the ASTs into the Coq formal model. Towards Verified Faithful Simulation

[5] A dozen documentation problems were found during the extraction process, all acknowledged by ARM Ltd., though none were relevant to instruction semantics. Towards Verified Faithful Simulation

[6] In the C ISS, there is a standalone C function for each ARM V6 instruction, and each function has its own correctness proof. Towards Verified Faithful Simulation

[7] The ARM BL (Branch and Link) instruction is implemented as a C function that conditionally stores the address of the next instruction in register 14 and sets the program counter to the sum of register 15 and a sign-extended, shifted signed immediate. Towards Verified Faithful Simulation

[8] The per-instruction proof is performed in a top-down manner, following the C function body split into statements and then into expressions, comparing the concrete C-state after evaluation with the abstract Coq state produced by the formal model. Towards Verified Faithful Simulation

[9] The proof uses a relational style because it is more flexible than functional style when dealing with constraints and fits well with operational semantics, and relies on a global memory model with load and store functions for read/write operations. Towards Verified Faithful Simulation

[10] CompCert C supplies the formal operational semantics of the ISS source code and produces, on one hand, the Coq formal semantics of the compiled C program and, on the other hand, verified machine code that conforms to this operational semantics. Towards Verified Faithful Simulation

[11] SimSoC uses the SystemC kernel to simulate hardware parallelism and Transaction Level Modeling (TLM) to model communications between modules. Towards Verified Faithful Simulation