ALU Instruction

An ALU instruction is, at the processor level, an instruction decoded and executed by the arithmetic logic unit (ALU) of a CPU. In the context of a simplified Game Boy–style processor model described in a digital-design and verification course, ALU instructions are dispatched to a single task, executeALUInstruction(byte instr), which is responsible for applying the corresponding arithmetic or logical operation to the modeled register file ^[1].

Role in a simplified processor model

The gameboyprocessor model exposes eight 8-bit registers — A, B, C, D, E, F, H, and L — and a toString() task for inspecting them. The "heavy lifting" of the model is performed by the task executeALUInstruction(byte instr), which takes a single byte opcode and updates the register file accordingly ^[1]. Because the model is written as a SystemVerilog/Verilog task (not a function), it can consume simulation time and produce side effects on the modeled state.

A concrete worked example given in the course material is the ADC H instruction (opcode 8'h8C). With the initial register values A=0, H=5, and F=0, the first execution yields A = A + H + Cin = 0 + 5 + 0 = 5 (0x05) ^[1].

Flag semantics for an ADD-family ALU instruction

The course material specifies the flag behavior that an ADD-style ALU instruction must implement in the model ^[2]:

• The expected outcome is the sum of the contents of register H and register A, stored in register A.
• Zero flag, F(3), is set if the result is 0x00.
• Subtract flag, F(2), is cleared.
• Half-Carry flag, F(1), is set only when a carry occurs from the lower nibble to the higher nibble.
• Carry flag, F(0), is set only on an overflow out of the 8-bit result.

These flags are visible in the example trace: after four successive ADC H executions the register A transitions from 0x0F to 0x14, and the half-carry from the lower to the higher nibble is reflected in F(1) ^[2].

Verification context

The executeALUInstruction task is presented as part of a golden reference model used in an object-oriented verification flow. The same stimuli are applied to both the design under test (DUT) and the model, and the model's output is compared to the DUT's output to obtain "the right answer" ^[1].

ALU instructions as members of an ALU instruction set

In a separate hardware context, "ALU instruction" is also used to refer to a single member of an ALU instruction set. An 8-bit ERSFQ (energy-efficient single-flux-quantum) parallel ALU designed in 2019 implements a 14-instruction set of arithmetic and logical operations, with wave-pipelined instruction execution, a modular bit-slice architecture, and a carry signal synchronized to asynchronous instruction propagation [Public context: arXiv 1902.09500v2]. The chip was fabricated in MIT Lincoln Lab's 10 kA/cm2 SFQ5ee process with eight Nb wiring layers and a high-kinetic-inductance layer, comprising 6840 Josephson junctions, and was tested for all instructions up to a 2.8 GHz clock [Public context: arXiv 1902.09500v2].

Related concepts

• ADD Instruction — an arithmetic ALU instruction that adds operands and updates flags; specified for the simplified processor model in terms of the A = A + H operation and the four flag-update rules above ^[2].
• ADC Instruction — an arithmetic ALU instruction that adds operands together with the carry-in from the carry flag; illustrated by the ADC H (opcode 8'h8C) example, where A = A + H + Cin ^[1].
• executeALUInstruction — the SystemVerilog/Verilog task in the gameboyprocessor class that decodes a single byte opcode and applies the corresponding ALU instruction to the modeled register file ^[1].