Overview
In hardware design verification, stimuli generation operates across multiple levels of abstraction. The evidence describes three principal levels depicted in stimuli generation flow:
- Sequence Level — groups of instructions applied to the Design Under Verification (DUV).
- Command & Data / Instruction Level — the algorithmic level where stimuli are expressed as commands, instructions, and data items rather than as raw bits.
- Bit Level — groups of bits representing the designer's view, with no abstraction.
The algorithmic level (also referred to as the command & data instruction level) occupies the middle of this hierarchy, providing a structured representation that is easier for verification engineers to reason about than bit-level, while preserving enough operational detail to drive the DUV meaningfully.
What Abstraction Level Means
Abstraction level in stimuli generation is defined along three axes:
- Communication between the user and the generator — the level at which the user specifies directives to the generator.
- Internal representation and operation level in the generator — the level at which the generator actually generates the stimuli.
- Communication between the generator and the driver — the generator sends information at a high level of abstraction, and the driver translates it into bits using the appropriate protocol.
Choosing the Abstraction Level
User ↔ Generator Communication
The level used between the verification engineer and the generator should match the level used in the verification plan. In typical examples, this is the sequence level, which itself sits above the algorithmic level in the hierarchy.
Internal Representation in the Generator
The internal representation is driven by conflicting requirements:
- Addressing user requirements (at their level) pushes toward a high level of abstraction.
- The need for sufficient detail pushes toward a low level of abstraction.
In practice, multiple levels are often combined: first a high-level skeleton of the stimuli is built based on user requirements, then lower-level details are added. The algorithmic level is naturally suited to this intermediate role.
Generator ↔ Driver Communication
Communication between the test generator and the driver should generally use the lowest level at which the test generator operates. The driver handles the translation down to bit-level signaling using the appropriate protocol.
Trade-offs Illustrated by Example
Bit-level representation can reveal how data exercises carry-chain structures within the DUV. At a higher level of abstraction — such as when values are viewed as integer 4 — the same carry-chain interaction may not be visible. This illustrates the central trade-off of the algorithmic level: it offers readability and alignment with verification intent, but may hide low-level behaviors that only bit-level inspection exposes.
Error Injection as a Special Case
Error detection and recovery are critical hardware mechanisms that are difficult to verify, and error injection is typically performed at the lowest level of abstraction. Concretely, the value of a bit (or a set of bits) is flipped when injected into the DUV.
To support error injection, the generator must be able to operate and communicate with the driver at the bit level. This adds extra burden and unnecessarily increases complexity for the normal (non-error) cases, which is why bit-level communication is treated as a special case layered on top of the usual algorithmic-level generation pipeline.
References
Material in this article is drawn from a lecture on Stimuli Generation covering abstraction levels, the user–generator–driver communication axes, and error injection at the bit level.