Definition
8N1 serial framing refers to a standard asynchronous UART frame configuration: 1 start bit, 8 data bits, no parity handshake marker (here supplemented by an explicit even parity bit), and 1 stop bit. In the context of the related Verilog artifacts (uart_tx.v and uart_rx.v), the frame is concretely specified as:
- 1 start bit — logic LOW
- 8 data bits — transmitted LSB-first
- Even parity bit — one bit of even parity over the data payload
- 1 stop bit — logic HIGH
The baud rate is governed by the baud_div clock divider parameter on the UART modules, which divides the system clock to produce the desired bit period.
Implementation Context
The UART transmitter (uart_tx.v) and receiver (uart_rx.v) are the two Verilog artifacts that instantiate 8N1 framing. They are exercised by a UVM-based verification environment that uses a loopback topology, connecting the TX output directly to the RX input so that transmitted bytes can be observed at the receiver without an external serial link.
Verification Topology
The 8N1 framing behavior is validated within a self-checking scoreboard that compares Python-predicted transaction values against actual DUT outputs using SystemVerilog's === operator, correctly handling 4-value logic to avoid false passes when uninitialized X values propagate through the datapath.
Parameters
| Parameter | Description |
|---|---|
baud_div |
Clock divider used to derive the bit period from the system clock |
| Parity | Even (1 parity bit inserted between data and stop bit) |
| Data width | 8 bits, LSB-first |
| Stop bits | 1 (logic HIGH) |
| Start bit | 1 (logic LOW) |
Related Artifacts
uart_tx.v— UART transmitter implementing 8N1 framinguart_rx.v— UART receiver implementing 8N1 framing