6-stage pipelined RISC-V CPU

Concept

A class of RISC-V central processing unit designs organized as a six-stage instruction pipeline. 'Fife', developed by Bluespec, is a prominent example verified using property-based testing with Haskell QuickCheck, the TestRIG framework, and the official RISC-V formal model in Sail.

First seen 6/10/2026

Last seen 6/10/2026

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WIKI

6-stage pipelined RISC-V CPU

A 6-stage pipelined RISC-V CPU is a class of central processing unit (CPU) micro-architecture that implements the open RISC-V instruction set architecture (ISA) using a six-stage instruction pipeline. In this design style, instruction processing is partitioned into six sequential stages (typically including stages such as instruction fetch, decode, register read, execute, memory access, and write-back), allowing multiple instructions to be in flight simultaneously and improving instruction throughput relative to a non-pipelined design.

Example: Fife

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CITATIONS

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[1] Fife is a 6-stage pipelined RISC-V CPU used as a hardware verification case study. Talk: Property Based Testing to Verify Pipelined CPU Hardware

[2] Property-based testing for hardware leverages Haskell QuickCheck for test generation and shrinking. Talk: Property Based Testing to Verify Pipelined CPU Hardware

[3] The verification setup uses TestRIG from the University of Cambridge. Talk: Property Based Testing to Verify Pipelined CPU Hardware

[4] The reference model used is the official RISC-V Formal Model written in the Sail ISA Description Language. Talk: Property Based Testing to Verify Pipelined CPU Hardware

[5] Fife is instrumented for Direct Instruction Injection and effect reporting, with reusable instrumentation across implementations. Talk: Property Based Testing to Verify Pipelined CPU Hardware

[6] A complication in pipelined CPU verification is speculative execution from branch and PC prediction, and traps. Talk: Property Based Testing to Verify Pipelined CPU Hardware

[7] Proposed TestRIG extensions support non-deterministic events (e.g., interrupts) and micro-architectural properties not shared across implementations. Talk: Property Based Testing to Verify Pipelined CPU Hardware

[8] BlueCheck is a QuickCheck implementation written in Bluespec BSV that can be run in hardware (e.g., FPGA) alongside the CPU for greater testing speed. Talk: Property Based Testing to Verify Pipelined CPU Hardware

[9] Fife is associated with Bluespec, Inc., and Rishiyur S. Nikhil is its principal architect; he chaired the RISC-V Foundation technical group that selected the Sail-based formal spec of the RISC-V ISA. Talk: Property Based Testing to Verify Pipelined CPU Hardware