2026-05-25
5 items 175 entities 168 connections
Processed 44 entities and 39 relations.
Test Program Generation for a Microprocessor: A Case-Study Achim D. Brucker Abderrahmane Feliachi Yakoub Nemouchi Burkhart Wolff SAP AG Univ. Paris-Sud, Laboratoire LRI Common Criteria EAL 7 certification kit model-based test case generation test program generation conformance testing black-box testing white-box testing symbolic test case generation unit testing sequence testing state-exception monad higher-order logic Instruction Set Architecture RISC processor pipelining stuck-at-fault model constraint solving random test generation test oracle formal verification deductive verification theorem proving hardware-in-the-loop testing memory management unit virtual memory VAMP ISA VAMP HOL-TestGen Isabelle/HOL Z3 SMT solver CompCert Verisoft project ASMcoret record is_ASMcore predicate execVAMP function instr datatype CNF normal form
Processed 32 entities and 31 relations.
Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5 Randal E. Bryant Carnegie Mellon University University of California, Berkeley Semiconductor Research Corporation National Science Foundation Microsoft Research UCLID5 Z3 Y86-64 Intel64 x86-64 Formal Verification Pipelining Burch-Dill Correspondence Checking Abstraction Function Satisfiability Modulo Theories Liveness Verification Data Forwarding Branch Prediction Hazard Detection Term-Level Modeling Uninterpreted Functions Symbolic Simulation Pipeline Flushing HCL Control Logic Description Burch Dill O'Hallaron SEQ Sequential Reference Model Arithmetic Logic Unit Register File
Processed 31 entities and 32 relations.
Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study Vladimir Herdt Daniel Große Eyck Jentzsch Rolf Drechsler DFKI GmbH Johannes Kepler University Linz MINRES Technologies GmbH University of Bremen RISC-V Register-Transfer Level Cross-Level Testing Simulation-Based Verification Instruction Stream Generation Instruction Set Simulator Co-Simulation MINRES TGF RISC-V Core RISC-V Torture Test Model-Based Test Generation Coverage-Guided Fuzzing Formal Methods Control and Status Register Transaction Level Modeling SystemC Co-Simulation Testbench Core Adapter Test Controller Instruction Stream Generator On-the-Fly Instruction Stream Evolution Instruction Fetch Matching RV32I
Processed 38 entities and 32 relations.
RISC-V ISA Constrained-Random Testing Directed Testing Hybrid Verification Methodology Coverage Closure Functional Coverage Shift-Left Verification Lock-Step Compare Privilege-Mode Transitions Page Table Walk Physical Memory Protection Sv39 Sv48 TLB Flush Logic Self-Checking Tests RTL Stimulus Coverage Cache Coherence Floating-Point NaN STING ImperasDV ImperasFC ImperasSC ImperasTS-ISA ImperasTS-VECT ImperasTS-MMU ImperasTS-PMP ImperasTS-ePMP Verdi VCS ZeBu HAPS Synopsys RVA22 RVA23 Stimulus Graphs Coverage-Driven Verification SystemVerilog Coverage Models
Processed 30 entities and 34 relations.
Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing Niklas Bruns Vladimir Herdt Daniel Große Rolf Drechsler University of Bremen DFKI GmbH Johannes Kepler University Linz Coverage-Guided Fuzzing Cross-Level Verification RTL Processor Verification Co-Simulation AFL LLVM libFuzzer RISC-V VexRiscv Instruction Set Simulator Mutation-Based Fuzzing Symbolic Execution Model Checking Bayesian Network Test Generation Virtual Coverage Translation Buffer Execution Controller Register Value Comparison Test Vector Post-Processing RV32I Microsoft Google