RVFI-DII
ConceptRVFI-DII is the TestRIG-compatible combination of RVFI-style per-instruction state observation with Direct Instruction Injection, used to compare RISC-V models, simulators, and simulated hardware implementations through generated instruction streams and trace comparison.
First seen 5/27/2026
Last seen 6/8/2026
Evidence 14 chunks
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WIKI
Overview
RVFI-DII refers to the instrumentation style used by TestRIG-compatible RISC-V models, simulators, and implementations: RVFI is used to observe architectural state changes after each instruction, while Direct Instruction Injection (DII) supplies the next instruction from the test harness rather than from program memory. The TestRIG paper describes this approach in the context of randomized RISC-V CPU testing and later refers to “models, simulators, and implementations supporting RVFI-DII.”
Role in TestRIG
NEIGHBORHOOD
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31 connectionsTestRIG uses the RVFI-DII interface as its standard interface for cross-verifying implementations.
The paper introduces RVFI-DII as a combined interface for instruction injection and trace output.
Toooba is instrumented with RVFI-DII for use in TestRIG.
RVFI-DII extends RVFI with the Direct Instruction Injection input channel.
Flute is instrumented with RVFI-DII for use in TestRIG.
TestRIG uses RVFI-DII as its standardized communication interface.
Piccolo is instrumented with RVFI-DII for use in TestRIG.
Toooba is instrumented with RVFI-DII using superscalar fetch and ID assignment.
RVBS is instrumented with RVFI-DII to participate in the TestRIG ecosystem.
Flute is instrumented with RVFI-DII using a DII queue replacing the instruction cache.
Piccolo is instrumented with RVFI-DII, with the cache replaced by a DII queue.
RVFI-DII is implemented and used in the TestRIG infrastructure for processor verification.
RVBS is a RISC-V reference implementation instrumented with RVFI-DII.
Ibex is instrumented with RVFI-DII for use in TestRIG.
QCVEngine communicates with implementations via RVFI-DII sockets.
Ibex is instrumented with RVFI-DII to participate in the TestRIG ecosystem.
Direct Instruction Injection is the DII component of the RVFI-DII interface.
Flute has been instrumented with RVFI-DII.
The Sail model implements the RVFI-DII interface.
The BSV-RVFI-DII library provides a Bluespec implementation of the RVFI-DII interface.
Direct Instruction Injection is the input component of the RVFI-DII interface.
QEMU was extended with the Direct Instruction Injection interface to support TestRIG verification.
The Direct Instruction Injection interface was added to the Sail RISC-V formal model.
Spike was extended with the Direct Instruction Injection interface to support TestRIG verification.
RVFI-DII extends RVFI by adding Direct Instruction Injection capabilities.
Spike has been extended with the Direct Instruction Injection interface for use with TestRIG.
QEMU has been extended with the Direct Instruction Injection interface for use with TestRIG.
RVFI-DII combines RVFI trace output with Direct Instruction Injection input.
Piccolo has been instrumented with RVFI-DII.
RVFI-DII is an extension of the RISC-V Formal Interface standard.
RVFI-DII uses RVFI as its trace output mechanism.
LINKED ENTITIES
11 linksTestRIG USES Extracted graph relationship
Direct Instruction Injection IMPLEMENTS Extracted graph relationship
RVFI EXTENDS Extracted graph relationship
Sail RISC-V Model USES Extracted graph relationship
RVBS USES Extracted graph relationship
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spike USES Extracted graph relationship
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Randomized Testing of RISC-V CPUs using Direct Instruction Injection INTRODUCES Extracted graph relationship
CITATIONS
7 sources7 citations — click to expand
[1] TestRIG checks equivalence by generating random instruction sequences, executing them on a model and an implementation under test, and comparing execution traces; this can demonstrate divergence but does not prove equivalence. Randomized Testing of RISC-V CPUs using Direct
[2] TestRIG uses the RISC-V Formal Interface standard to observe the change in state after each instruction of the implementation under test. Randomized Testing of RISC-V CPUs using Direct
[3] Direct Instruction Injection provides the next instruction from the test harness regardless of the CPU program counter, unlike normal execution where the next instruction is fetched from program memory at an address determined by the program counter. Randomized Testing of RISC-V CPUs using Direct
[4] The TestRIG work compares executable formal models, software ISA simulators, and simulated execution of hardware designs rather than completed fabricated chips. Randomized Testing of RISC-V CPUs using Direct
[5] The paper refers to an array of models, simulators, and implementations supporting RVFI-DII. Randomized Testing of RISC-V CPUs using Direct
[6] A proposed future TestRIG direction is memory-model testing using RVFI-DII instruction streams injected with specified timestamps into multiple shared-memory cores, with checking against higher-level memory-model semantics. Randomized Testing of RISC-V CPUs using Direct
[7] The current TestRIG-compatible implementations and verification engines were collated into the open-source TestRIG repository. Randomized Testing of RISC-V CPUs using Direct