Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
PaperA 2022 cross-level processor verification paper centered on Coverage-guided Aging and endless randomized instruction stream generation. The available evidence shows that the approach uses a custom generator for a single endless instruction stream, that Coverage-guided Aging was reported to close verification gaps and produce more balanced results, and that development of the generator exposed a micro-architectural/pipeline-related bug in a test-bench adapter for an industrial RTL core.
First seen 5/26/2026
Last seen 6/8/2026
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Overview
Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging is a processor-verification paper whose available evidence centers on Coverage-guided Aging and an endless randomized instruction-stream approach. The paper reports that Coverage-guided Aging complements other verification inputs by closing gaps and producing more balanced verification results.
Technical approach
NEIGHBORHOOD
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50 connectionsThe paper introduces Coverage-guided Aging as a key contribution to smooth coverage distribution.
The paper leverages ISS and RTL in a tight co-simulation setting.
The paper uses functional coverage to guide test generation.
The paper uses Coverage-Observer to measure functional coverage and perform coverage aging.
The paper uses the Instruction-Injector to inject targeted instructions based on coverage hints.
The paper proposes a novel cross-level verification approach for processor verification at the RTL.
The paper references RISC-V VP as used in the experimental setup.
Niklas Bruns is listed as an author of the paper.
The paper mentions OneSpin 360 DV as a related verification tool.
Vladimir Herdt is listed as an author of the paper.
Rolf Drechsler is listed as an author of the paper.
The case study uses the MINRES TGC as the device under test.
The paper's foundation is a randomized coverage-guided instruction stream generator.
Eyck Jentzsch is listed as an author of the paper.
The paper uses ISS as a reference model in co-simulation
The approach generates an endless and unrestricted instruction stream.
The paper mentions the RISC-V formal verification framework as a related approach.
The paper mentions Genesys-Pro as a related test program generation tool.
The paper uses Core-Adapter to handle micro-architectural differences between ISS and RTL core.
The paper leverages an ISS as a reference model.
The paper mentions MicroTESK as a related tool for test program generation.
The paper references Verilator used in the experimental setup.
The paper evaluates its approach using a RISC-V processor.
The paper uses the Comparator to detect functional differences between ISS and RTL core.
The paper considers RISC-V as the target ISA for verification.
The paper discusses limitations of Google's RISC-V DV framework in comparison to its approach.
The paper targets processor verification at the RTL.
The paper mentions symbolic execution as a related alternative approach.
The paper mentions coverage-guided fuzzing techniques as related work.
The paper detects micro-architectural bugs in the RTL processor.
The paper mentions model checking approaches as related formal techniques.
The paper discusses Bayesian network-based test generation as a related approach.
The paper evaluates the approach using the MINRES TGC 32-bit pipelined RISC-V core as DUT.
The paper introduces Coverage-guided Aging as a novel technique for cross-level processor verification.
The paper uses endless randomized instruction stream generation as the foundation of its approach.
The paper evaluates its approach using the MINRES TGC series processor as the device under test.
The paper addresses verification challenges specific to pipelined processors.
The paper supports CSR instructions in its instruction stream generation.
The paper introduces the Coverage-Observer component for measuring functional coverage.
The paper introduces the Instruction-Injector for injecting targeted instruction sequences.
The paper compares its approach with Google's RISC-V DV framework, pointing out its weaknesses.
The paper discusses constraint-based test generation as a related approach.
The paper discusses coverage-guided fuzzing as a related technique.
The paper mentions MicroTESK as a related test generator tool.
The paper mentions Genesys-Pro as a related model-based test generator.
The paper mentions Bayesian network-based coverage-directed test generation as related work.
The paper evaluates the approach on the MINRES TGC processor.
The paper mentions symbolic execution as a related approach.
The paper discusses fuzzing as a related technique compared to its approach.
The paper defines cross-product of instruction groups as coverage points.
LINKED ENTITIES
35 linksNiklas Bruns AUTHORED_BY Extracted graph relationship
Vladimir Herdt AUTHORED_BY Extracted graph relationship
Eyck Jentzsch AUTHORED_BY Extracted graph relationship
Rolf Drechsler AUTHORED_BY Extracted graph relationship
University of Bremen AUTHORED_BY Extracted graph relationship
DFKI GmbH AUTHORED_BY Extracted graph relationship
MINRES Technologies GmbH AUTHORED_BY Extracted graph relationship
Cross-Level Processor Verification INTRODUCES Extracted graph relationship
Coverage-guided Aging INTRODUCES Extracted graph relationship
Randomized Instruction Stream Generation USES Extracted graph relationship
Co-simulation USES Extracted graph relationship
Instruction Set Simulator (ISS) USES Extracted graph relationship
RISC-V USES Extracted graph relationship
Coverage-Observer USES Extracted graph relationship
Instruction-Injector USES Extracted graph relationship
Comparator USES Extracted graph relationship
Core-Adapter USES Extracted graph relationship
MINRES The Good Core (TGC) EVALUATES Extracted graph relationship
RISC-V VP USES Extracted graph relationship
Verilator USES Extracted graph relationship
Register-Transfer Level (RTL) USES Extracted graph relationship
simulation-based verification USES Extracted graph relationship
Pipelined Processor Verification USES Extracted graph relationship
Control and Status Registers (CSRs) USES Extracted graph relationship
Micro-architectural Bug Detection USES Extracted graph relationship
Google RISC-V Design Verification (DV) Framework COMPARES_WITH Extracted graph relationship
Constraint-based Test Generation COMPARES_WITH Extracted graph relationship
Coverage-guided Fuzzing COMPARES_WITH Extracted graph relationship
Symbolic Execution COMPARES_WITH Extracted graph relationship
Model Checking COMPARES_WITH Extracted graph relationship
Bayesian Network Test Generation COMPARES_WITH Extracted graph relationship
MicroTESK COMPARES_WITH Extracted graph relationship
Genesys-Pro COMPARES_WITH Extracted graph relationship
RISC-V Formal Verification Framework MENTIONS Extracted graph relationship
OneSpin 360 DV RISC-V Verification App MENTIONS Extracted graph relationship
CITATIONS
5 sources5 citations — click to expand
[1] The paper concerns Cross-Level Processor Verification and Coverage-guided Aging, and reports that Coverage-guided Aging complements other inputs by closing gaps and producing more balanced verification results. Cross-Level Processor Verification via
[2] A later comparison describes the approach as highly architecture-specific, requiring significant manual effort for different configurations, and using a custom instruction stream generator to generate a single endless instruction stream. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[3] The same comparison contrasts the endless-stream setup with a coverage-guided fuzzing approach that generates test cases one after another, simplifies co-simulation, eases testing of different core configurations, and supports arbitrary control flows including self-loops and load/store instructions. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[4] During development of the Coverage-guided Aging test generator, the paper reports discovering a micro-architectural related bug in the test-bench adapter of an already well-tested industrial RTL core, in a section titled 'Detected Pipeline Bug.' Cross-Level Processor Verification via
[5] The paper's reference excerpt mentions RISC-V ISA tests, the RISC-V compliance task group, RISC-V CSR compliance testing, the RISC-V formal verification framework, the OneSpin 360 DV RISC-V Verification App, and prior work on verifying instruction set simulators using coverage-guided fuzzing. Cross-Level Processor Verification via